The present invention relates to memory systems. More specifically, the present invention relates to the control of read, write and pre-charge operations in a static random access memory (SRAM) system.
FIG. 1 is a schematic diagram of a conventional SRAM cell 100. SRAM cell 100 includes access transistors 101-102, cross-coupled inverters 103-104, word line 110 and bit lines 111-112. Inverters 103-104 are formed by p-channel transistors 105-106 and n-channel transistors 107-108.
FIG. 2 is a waveform diagram illustrating the conventional operation of SRAM cell 100. SRAM cell 100 operates synchronously in response to a system clock signal, CLK. Prior to cycle C1, bit lines 111 and 112 are pre-charged to the Vdd supply voltage and word line 110 is held at 0 Volts (ground). A write operation is initiated at the rising edge of clock cycle C1. After a time period ta, a high WL signal is asserted on word line 110, thereby turning on access transistors 101 and 102. The word line signal WL is asserted as early as possible after the write operation is detected. In addition, a data signal having a full signal swing is applied to bit lines 111 and 112. That is, one of bit lines 111-112 is held at the Vdd supply voltage, and the other one of bit lines 111-112 is pulled down to ground. Because access transistors 101 and 102 are turned on, the data value on bit lines 111-112 is latched into cross-coupled inverters 103-104.
The word line signal WL is asserted high for a time period tb, which is long enough to insure that the data value on bit lines 111-112 is stored in cross-coupled inverters 103-104. At the end of time period tb, the word line signal WL is de-asserted low. After access transistors 101-102 have been turned off by the low word line signal WL, the Vdd supply voltage is applied to both of bit lines 111-112, thereby causing these bit lines to begin pre-charging to the Vdd supply voltage. Note that one of bit lines 111-112 is already at the Vdd supply voltage, while the other one of bit lines 111-112 must be pre-charged to the Vdd supply voltage starting from 0 Volts. Pre-charging bit lines 111-112 to the Vdd supply voltage after a write operation requires a pre-charge time period tc. The pre-charge time period tc defines the minimum time required between de-asserting word line signal WL at the end of a write operation, and asserting word line signal WL at the beginning of a subsequent operation.
A read operation is initiated at the rising edge of clock cycle C2. After the time period ta, a logic high word line signal WL is asserted on word line 110, thereby turning on access transistors 101 and 102. Note that the word line signal WL is not asserted until after bit lines 111-112 have had sufficient time to be pre-charged to the Vdd supply voltage. That is, pre-charge time period tc must be completed before word line signal WL can be asserted. If the word line signal WL is asserted before bit lines 111-112 have been pre-charged to the Vdd supply voltage, a read disturb condition may exist, resulting in a slower access time or a failed read operation.
The word line signal WL is again asserted high for the time period tb, which has a duration sufficient to insure that the data value stored in SRAM cell 100 is read from cross-coupled inverters 103-104. During the read operation, one of bit lines 111-112 remains at the Vdd supply voltage, and the other one of bit lines 111-112 is pulled down to a voltage which is less than the Vdd supply voltage. A sense amplifier (not shown) senses this small difference to identify the data value stored in SRAM cell 100.
At the end of time period tb, the word line signal WL is de-asserted low. After access transistors 101-102 have been turned off by the low word line signal WL, the Vdd supply voltage is applied to both of bit lines 111-112, thereby causing these bit lines to begin pre-charging to the Vdd supply voltage. Note that one of bit lines 111-112 is already at the Vdd supply voltage, while the other one of bit lines 111-112 is pre-charged to the Vdd supply voltage starting from a voltage slightly below the Vdd supply voltage. Consequently, the pre-charge following a read operation can be completed in less time than a pre-charge following a write operation. However, the pre-charge time period tc is still provided at the end of the read operation.
A write operation is initiated at the rising edge of clock cycle C3. The write operation during clock cycle C3 is similar to the write operation during clock cycle C1. Thus, after the time period ta, a high WL signal is asserted on word line 110, thereby turning on access transistors 101 and 102. Again, the pre-charge time period tc elapses between the time that the word line signal WL is de-asserted during the read cycle and the time that the word line signal WL is asserted during the write cycle.
The width of the word line pulse WL (i.e., tb) is fixed, and is the same for both read and write operations. In addition, the time period ta between the rising edge of the clock signal and the rising edge of the word line signal WL is fixed, and is the same for read and write operations. Finally, the time period tc between the falling edge of the word line signal WL and the next rising edge of the word line signal WL is the same regardless of the nature of the corresponding operations (i.e., read or write operations).
In the described example, the cycle time (tcyc) for SRAM cell 100 is equal to the duration tb of the word line pulse WL plus the pre-charge time period tc. For example, the word line pulse width tb may have a value of 4 nsec and pre-charge time period tc may have a value of 2 nsec, such that the cycle time tcyc is equal to 6.0 nsec. It would be desirable to have a system and a method for reducing the cycle time of SRAM cell 100.
Accordingly, the present invention provides a method of accessing an SRAM cell that includes the steps of: (1) determining whether an access to the SRAM cell is a read access or a write access, (2) applying a first word line pulse having a first width to the word line if the access is a read access, and (3) applying a second word line pulse having a second width to the word line if the access is a write access, wherein the first width is different than the second width. For example, the width of the first word line pulse required to perform a read access may be greater than the width of the second word line pulse required to perform a write access. The cycle time of the SRAM cell is reduced by applying word line pulses having only the necessary widths.
In another embodiment, the method further includes the steps of: pre-charging a pair of bit lines coupled to the SRAM cell for a first pre-charge period after de-asserting the first word line pulse, and pre-charging the pair of bit lines for a second pre-charge period after de-asserting the second word line pulse, wherein the first pre-charge period is different than the second pre-charge period. For example, the first pre-charge period will be less than the second pre-charge period if it takes less time to pre-charge after a read operation than after a write operation. Again, the cycle time of the SRAM cell is reduced by providing pre-charge operations having only the necessary periods. Another embodiment provides a method of operating an SRAM system in which read operations are prohibited from being initiated during consecutive cycles of the SRAM system. This method includes the steps of: (1) applying a word line pulse to a word line of the SRAM system for a first period if the access is a read access, (2) applying a word line pulse to a word line of the SRAM system for a second period if the access is a write access, wherein the first period is different than the second period, and (3) pre-charging a pair of bit lines of the SRAM system for a pre-charge period after applying the word line pulse during the write access, wherein the cycle time of the SRAM system is equal to the sum of the first period, the second period and the pre-charge period. Alternatively, the cycle time of the SRAM system can be equal to one half of the sum of the first period, the second period and the pre-charge period.
In this embodiment, the cycle time is reduced by the pre-charge period previously required after a read operation. Additional time does not have to be provided in the cycle time for pre-charging after a read operation because only a write operation or no operation can follow a read operation. If a write operation follows a read operation, the write drivers are strong enough to overcome the small voltage differences that may remain on the bit lines after a read operation. If no operation follows a read operation, then the read pre-charge operation has an entire no-operation cycle to pre-charge the bit lines.
The present invention will be more fully understood in view of the following description and drawings.